Elektronika - baza wiedzy

Złącze ISA



ISA = Industry Standard Architecture

PinNazwaOpis
A1/I/O CH CKI/O channel check; active low=parity error
A2D7Data bit 7
A3D6Data bit 6
A4D5Data bit 5
A5D4Data bit 4
A6D3Data bit 3
A7D2Data bit 2
A8D1Data bit 1
A9D0Data bit 0
A10I/O CH RDYI/O Channel ready, pulled low to lengthen memory cycles
A11AENAddress enable; active high when DMA controls bus
A12A19Address bit 19
A13A18Address bit 18
A14A17Address bit 17
A15A16Address bit 16
A16A15Address bit 15
A17A14Address bit 14
A18A13Address bit 13
A19A12Address bit 12
A20A11Address bit 11
A21A10Address bit 10
A22A9Address bit 9
A23A8Address bit 8
A24A7Address bit 7
A25A6Address bit 6
A26A5Address bit 5
A27A4Address bit 4
A28A3Address bit 3
A29A2Address bit 2
A30A1Address bit 1
A31A0Address bit 0
B1GNDGround
B2RESETActive high to reset or initialize system logic
B3+5V+5 VDC
B4IRQ2Interrupt Request 2
B5-5VDC-5 VDC
B6DRQ2DMA Request 2
B7-12VDC-12 VDC
B8/NOWSNo WaitState
B9+12VDC+12 VDC
B10GNDGround
B11/SMEMWSystem Memory Write
B12/SMEMRSystem Memory Read
B13/IOWI/O Write
B14/IORI/O Read
B15/DACK3DMA Acknowledge 3
B16DRQ3DMA Request 3
B17/DACK1DMA Acknowledge 1
B18DRQ1DMA Request 1
B19/REFRESHRefresh
B20CLOCKSystem Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
B21IRQ7Interrupt Request 7
B22IRQ6Interrupt Request 6
B23IRQ5Interrupt Request 5
B24IRQ4Interrupt Request 4
B25IRQ3Interrupt Request 3
B26/DACK2DMA Acknowledge 2
B27T/CTerminal count; pulses high when DMA term. count reached
B28ALEAddress Latch Enable
B29+5V+5 VDC
B30OSCHigh-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)
B31GNDGround
   
C1SBHESystem bus high enable (data available on SD8-15)
C2LA23Address bit 23
C3LA22Address bit 22
C4LA21Address bit 21
C5LA20Address bit 20
C6LA18Address bit 19
C7LA17Address bit 18
C8LA16Address bit 17
C9/MEMRMemory Read (Active on all memory read cycles)
C10/MEMWMemory Write (Active on all memory write cycles)
C11SD08Data bit 8
C12SD09Data bit 9
C13SD10Data bit 10
C14SD11Data bit 11
C15SD12Data bit 12
C16SD13Data bit 13
C17SD14Data bit 14
C18SD15Data bit 15
D1/MEMCS16Memory 16-bit chip select (1 wait, 16-bit memory cycle)
D2/IOCS16I/O 16-bit chip select (1 wait, 16-bit I/O cycle)
D3IRQ10Interrupt Request 10
D4IRQ11Interrupt Request 11
D5IRQ12Interrupt Request 12
D6IRQ15Interrupt Request 15
D7IRQ14Interrupt Request 14
D8/DACK0DMA Acknowledge 0
D9DRQ0DMA Request 0
D10/DACK5DMA Acknowledge 5
D11DRQ5DMA Request 5
D12/DACK6DMA Acknowledge 6
D13DRQ6DMA Request 6
D14/DACK7DMA Acknowledge 7
D15DRQ7DMA Request 7
D16+5 V 
D17/MASTERUsed with DRQ to gain control of system
D18GNDGround